The present invention generally relates to frequency synthesis, and particularly relates to PLL-based frequency synthesis.
Radio frequency (RF) communications equipment, such as mobile terminals within a wireless communication system, routinely uses precise frequency reference signals in receive and transmit operations. Often, such reference signals are used to derive additional signals, possibly of higher or lower frequency, but with the stability and accuracy inherent in the reference signal. This frequent need to slave the frequency or timing of one signal to another, or to monitor the phase or frequency difference between two signals, gives rise to specialized circuits, such as the phase-locked loop (PLL).
A general PLL configuration has a controllable oscillator generating an output signal, a detector generating an error signal based on the phase or frequency difference between a feedback signal derived from the output signal and an input reference signal. The PLL generally includes some type of control circuit to adjust the oscillator based on the error signal generated by the detector. In this manner, the oscillator""s output signal may be xe2x80x9clockedxe2x80x9d to the input reference signal. By setting frequency dividing ratios between the reference and the feedback signals, the output signal may be made to have a higher or lower frequency than the input signal. A mobile terminal might generate a stable reference signal with a precisely fixed frequency, and then use a PLL-based frequency synthesizer to generate higher frequency signals used in transmit signal modulation and received signal down conversion.
Although PLL circuits vary widely in their implementation, the detector generally provides one or more output signals that, in general, are driven by the phase or frequency difference between two periodic input signals. Often, these two input signals represent a reference clock signal and an adjustable clock signal that is locked to the reference clock signal by operation of the PLL. When the detector""s output signal(s) are generated as a function of the phase difference between the two input signals, the output signals accurately reflect the phase difference between the two input signals only when that difference is within a defined range. Generally, phase detectors used within PLL circuits cannot linearly detect when the phase difference between its two input signals is greater than xc2x12xcfx80 radians.
The present invention is a system and method for reducing phase detection error in a phase/frequency detector (PFD) arising from cycle slip. The PFD compares arrival time differences between respective clock edges in two input signals and provides control outputs based on the phase difference between these clock edges. When the, PFD misses a clock edge in either input signal, cycle slip occurs. Phase-reset circuits couple the two input signals to the PFD and operate as input frequency divider circuits, providing the PFD with a sub-harmonic of each input signal. Each phase-reset circuit normally operates as an up (or down) counter, providing one output clock cycle to the PFD for every N input signal clock cycles. When presented with an indication of cycle slip, however, the phase-reset circuit sets its divide-by counter to a value that causes the next input signal clock cycle to produce an output clock cycle. This action results in the cycle slip causing substantially less than the 2xcfx80 radians per missed cycle of phase error that otherwise manifests itself in the PFD control outputs.
Generally, the PFD operates as part of a PLL and provides an xe2x80x9cupxe2x80x9d and a xe2x80x9cdownxe2x80x9d control signal to charge pump circuitry that ultimately increases or decreases the control voltage applied to a voltage controlled oscillator. One of the two input signals to the PFD is derived from the VCO""s output signal, and the other input signal serves as a reference against which the PLL controls the output signal. By including phase-reset circuits on the front-end of the PFD, the up/down control signal error arising from cycle slip can be reduced substantially. In general, the amount of error reduction depends upon the resolution the phase-reset circuit""s digital counter. The reduced cycle slip error allows the PFD to control the associated charge pump circuit such that it remains near its maximum duty cycle for large frequency errors between the two input signals. Operation of the charge pump or pumps within the PLL in this manner tends to reduce the lock time of the PLL, improving overall performance in frequency synthesis functions based on the PLL.